Cisco Offcampus Drive for 2023, 2024 Batches | Cisco Job Alert 2023
| JOB | DETAILS |
|---|---|
| Company | Cisco |
| Role | ASIC Design and Verification, ASIC Physical Design, ASIC DFT Engineer |
| Batch | 2023, 2024 |
| Education | BE / B.TECH / ME / M.TECH |
| Salary | 7 LPA - 14 LPA |
| Experience | - |
| Last Date | 2nd Mar 2023, 4:00 PM |
| Location | Bangalore |
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JOB DESCRIPTION
Cisco India is seeking applications from students interested in working as ASIC Engineers as a part of Cisco Silicon One group. If you have a passion for technology and consider this to be an exciting career path, please click the link below to apply. This opening is for Engineering students.
For Summer Internship (2024 Passing out Students)
To learn more about the job role & eligibility criteria, click on the job description for 2024 batch below
To Register, click On the apply button for 2024 batch below
For Full Time Role (2023 Passing out Students)
To learn more about the job role & eligibility criteria, click on the job description for 2023 batch below
To Register, click On the apply button for 2023 batch below
For Summer Internship (2024 Passing out Students)
To learn more about the job role & eligibility criteria, click on the job description for 2024 batch below
To Register, click On the apply button for 2024 batch below
For Full Time Role (2023 Passing out Students)
To learn more about the job role & eligibility criteria, click on the job description for 2023 batch below
To Register, click On the apply button for 2023 batch below
FOR 2023 BATCH:
Who You Are?
- Students passing out in 2023 and Pursuing Bachelor / Master degree in Electronics Engineering /Micro Electronics/VLSI.
- Ability to manage multiple tasks and work toward long-term goals.
- Solid understanding of engineering fundamentals and technical problem-solving skills.
- Experience in establishing and sustaining strong relationships with the extended team.
- Excellent communication skills (verbal and written).
- Knowledge in Hardware design, the test/verification environment is designed using an object-oriented framework designed in using UVM so you will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as SystemVerilog HDL / C / C++ / Python
- You will aid in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components using UVM.
- Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based Verilog simulators.
- Problem solving skills and out-of-the-box thinking to create area and power efficient hardware designs as well as reusable UVM classes for the verification and simulation environments.
- Physical Implementation of blocks, clock trees, Static Timing Analysis, DFT, Logic Equivalence Checks are part of the Physical Design specialist profile.
- Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members.
FOR 2024 BATCH:
Who You Are?
- Passing out in 2024 and holding a Bachelor / Master degree in Electronics Engineering/ Micro Electronics/ VLSI.
- Ability to manage multiple tasks and work toward long-term goals.
- Solid understanding of engineering fundamentals and technical problem-solving skills.
- Experience in establishing and sustaining strong relationships with the extended team.
- Excellent communication skills (verbal and written).
- Knowledge in Hardware design, the test/verification environment is designed using an object-oriented framework designed in using UVM so you will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as SystemVerilog HDL / C / C++ / Python
- You will aid in the architecture of the test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components using UVM.
- Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based Verilog simulators.
- Problem solving skills and out-of-the-box thinking to create area and power efficient hardware designs as well as reusable UVM classes for the verification and simulation environments.
- Physical Implementation of blocks, clock trees, Static Timing Analysis, DFT, Logic Equivalence Checks are part of the Physical Design specialist profile.
- Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members.
JOB DESCRIPTION FOR 2023 BATCH: CLICK HERE
JOB DESCRIPTION FOR 2024 BATCH: CLICK HERE
